 Hello friends, I hope you all are doing great. In today’s tutorial, we will have a look at Transistor BJT Voltage Divider Bias. The most common and normally used method for biasing a transistor is a voltage divider bias circuit. It consists of some resistances for division or voltages and distribution among resistance at a proper level.
Voltage divider bias also is known as emitter current bias. In today’s post we will have a detailed look at its circuit, working and other related factors. You will also learn as biasing linear transistor operation through using a single-source resistance voltage divider. So, let’s get started with Transistor BJT Voltage Divider Bias

#### Transistor BJT Voltage Divider Bias

• In below figure you can see the circuit which using VCC as a single bias source.
• To make simple representation for VCC instead of battery symbol a line with a circle is shown.
• The dc bias voltage at the base terminal of the transistor can be provided through resistive voltage divider circuit which has two resistances denoted as R1 and R2.
• VCC is a dc collector supply voltage source. There are 2 paths for current between point A and ground one from the resistance R2 and second from the base-emitter junction of transistor and resistance RE.
• Usually, voltage divider bias circuitry is created as IB is less than the current flowing through the resistance R2 that is I2.

VB=[R2/(R1+R2)]VCC

• After finding the value of VB you can determine the voltage and current in the circuitry as.

VE =VB -VBE

and

IC=IE=VE/RE

Hence

VC =VCC -ICRC

• After calculating VC and VE you can find VCE.

VCE = VC – VE

DC Input Resistance at the Transistor Base

• The value of dc input resistance of the transistor is directly proportionate to the βDC so its value will be different for a different transistor.
• When the transistor functions in its linear region the emitter current will be βDCIB.
• When we observed the emitter resistance from the base circuitry the resistance looks greater than its real value due to dc current gain of a transistor.

Which is,

RIN(BASE)= VB/IB = VB /(IE/βDC).

RIN(BASE) =βDCVB/IE

• It is effective to load on the voltage divider circuit as shown in the figure.
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• You can rapidly guess the loading effect by relating RIN(BASE) to the resistor R2 in the voltage divider.
• If RIN(BASE) is at least 10 times greater than R2, the loading effect will be ten percent or less and the voltage divider is stiff.
• If RIN(BASE) is less than 10 times R2, it must be connected in parallel with R2. #### Thevenin’s Theorem Applied to Voltage-Divider Bias

• Now we will apply Thevenin theorem to for analyzation of voltage divider biased transistor circuit for loading effect of base current.
• First take an equivalent base-emitter circuitry shown in figure denoted as (a)by applying Thevenin theorem.
• By observing from the base terminal bias circuitry can reconstruct as denoted in figure as (b).
• Apply thevenin theorem on left side of point A with VCC substituted with a short to ground and removed the transistor from the circuitry.
•  The value of the voltage at point A with respect to ground terminal is given as.

VTH=[R2/(R1+R2)]VCC

the value of resistance is

RTH=R1R2/R1+R2

• The Thevenin correspondent of the bias circuitry, associated to the transistor base, is shown in the beige box denoted as (c).
• By applying KVL we get.

VTH – VRTH – VBE – VRE = 0

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• By applying ohm law we have.

VTH = IBRTH + VBE + IERE

• By putting IE/βDC for IB

VTH = IE(RE + RTH/βDC) + VBE

• By solving for IE we have.

IE=(VTH-VBE)/RE-RTH/βDC

• If the value of RTH/βDC is less than the RE the output is like to the voltage divider without load.
• Voltage-divider bias is extensively used due to fine bias stability is obtained with a single supply voltage. #### Voltage-Divider Biased PNP Transistor

• We know that for PNP transistors there is a need for opposite biasing polarities. It can be obtained through the negative collector supply voltage as denoted in figure by (a).
• It can also obtained through providing positive voltage to the emitter as shown in the figure by (b).
• The analyzing process is alike to the NPN transistor circuit applying Thevenin and KVL as described in these steps according to given figure.
• After applying KVL about the base-emitter circuit you have.

VTH + IBRTH – VBE + IERE = 0

• Applying Thevenin theorem.

VTH=(R2/R1+R2)VCC

RTH=R1R2/R1+R2

Base current is given as.

IB=IE/βDC

• The equation for IE is given as.

IE=(-VTH+ VBE)/(RE-RTH/βDC)

• For circuit denoted as (b) the analysis is given as.

-VTH + IBRTH – VBE + IERE – VEE = 0

VTH =(R1/R1 + R2)VEE

RTH=R1R2/R1 + R2

IB = IE/βDC

• The equation for emitter current will be.

IE=VTH +VBE-VEE/(RE +RTH/βDC) So, friends, it is a detailed post about Transistor BJT Voltage Divider Bias if you have any questions ask in comments. Thanks for reading. See you in next post have a good day. thanks for reading.